vhdl - Why does Modelsim 10 not compile older code? -

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i upgraded modelsim 10 , when recompiled code, 30 out of 37 compiled. wouldn't compile had common error 

no feasible entries infix operator "&"

i included packages std_logic, change bits std_logics, , magically fixes problem on first recompiling (a rare sight me). question why did new compiler (if new) not accept bit & unsigned(n downto 0). kind of new standard force hdl coders use more abstraction? saw similar question solved problem, want know why compilation different.

could new modelsim uses different default settings (e.g. -2008 instead of -87)?


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